An area-efficient VLSI architecture for decoding of Reed-Solomon codes

This paper presents a new pipelined VLSI array for decoding Reed-Solomon (RS) codes. The architecture is designed based on the modified time-domain BerlekampMassey algorithm incorporated with the remainder decoding concept. A prominent feature of the proposed system is that, for a t-error-correcting RS code with block length n, it involves only 2t consecutive symbols to compute a discrepancy value in the decoding process, instead of n consecutive symbols used in the previous RS decoders based on the same algorithm without using the remainder decoding concept. The proposed RS decoder reaches an average decoding rate of one data symbol per clock cycle. As compared to a similar pipelined RS decoder with the same decoding rate, it gains significant improvements in hardware complexity and latency.